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1 of 15 091599 features synchronizes loop?timed and system?timedt1 data streams two?frame buffer depth; slips occur on frameboundaries output indicates when slip occurs buffer may be recentered externally ideal for 1.544 to 2.048 mhz rate conversion interfaces to parallel or serial backplanes extracts and buffers robbed?bit signaling inhibits signaling updates during alarm or slipconditions integration feature ?debounces? signaling slip?compensated output indicates whensignaling updates occur compatible with ds2180a t1 transceiver surface mount package available, designatedDS2176Q industrial temperature range of ?40c to+85c available, designated ds2176n pin assignment descriptionthe ds2176 is a low?power cmos device specifically designed for synchronizing receive side loop? timed t?carrier data streams with system side timing. the device has several flexible operating modes which simplify interfacing incoming data to parallel and serial tdm backplanes. the device extracts, buffers and integrates abcd signaling; signaling updates are prohibited during alarm or slip conditions. the buffer replaces extensive hardware in existing applications with one ?skinny? 24?lead package. application areas include digital trunks, drop and insert equipment, transcoders, digital cross?connects (dacs), private network equipment and pabx?to?computer interfaces such as dmi and cpi. ds2176 t1 receive buffer www.dalsemi.com 23 rclk a c d schclk sm0 sm1 vss vdd scklsel syclk sser slip sbit8 smsync sigfrz sfsync aln fms s/p 1 2 3 4 5 6 7 8 9 10 11 12 24 22 21 20 19 18 17 16 15 14 13 rmsyn rser b sigh 24-pin 300 mil dip 28-pin plcc ab nc nc c d sserslip sbit8 ncnc smsync schclk sigfrz rser rclk rmsync sigh vdd scklsel sysclk sm0 sm1 vss s/p fms aln sfsync 2524 23 22 21 20 19 56 7 89 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 downloaded from: http:///
ds2176 2 of 15 ds2176 block diagram figure 1 downloaded from: http:///
ds2176 3 of 15 pin description table 1 pin symbol type description 1 sign i signaling inhibit. when low, abcd signaling updates are disabled for a period determined by sm0 and sm1, or until returned high. 2 rmsync i receive multifram sync. must be pulsed high at multiframe boundaries to establish frame and multiframe alignment. 3 rclk i receive clock. primary 1.544 mhz clock. 4 rser i receive serial data. sampled on falling edge of rclk. 56 7 8 ab c d o robbed-bit signaling outputs. 9 schclk o system channel clock. transitions high on channel boundaries; useful for serial to parallel conversion of channel data. 1011 sm0sm1 i signaling modes 0 and 1. select signaling supervision technique. 12 v ss ? signal ground. 0.0 volts. 13 s/ p i serial/parallel select. tie to v ss for parallel backplane applications, to v dd for serial. 14 fms i frame mode select. tie to v ss to select 193s(d4) framing to v dd for 193e (extended). 15 aln i align. recenters buffer on next system side frame boundary when forced low. 16 sfsync i system frame sync. rising edge establishes start of frame. 17 sigfrz o signaling freeze. when high, indicates signaling updates have been disabled internally via a slip or externally by forcing sigh low. 18 smsync o system multiframe sync. slip-compensated multiframe output; indicates when signaling updates are made. 19 sbit8 o system bit 8. high during the lsb time of each channel. used to reinsert extracted signaling into outgoing data stream. 20 slip o frame slip. active low, open collector output. held low for 65 sysclk cycles when a slip occurs. 21 sser o system serial out. updated on rising edge of sysclk. 22 sysclk i system clock. 1.544 or 2.048 mhz data clock. 23 sclksel i system clock select. tie to v ss for 1.544 mhz applications, to v dd for 2.048 mhz. 24 v dd ? positive supply. 5.0 volts. downloaded from: http:///
ds2176 4 of 15 overviewthe ds2176 performs two primary functions: 1) synchronization of received t1 pcm data (looped timed) to host backplane frequencies; 2) supervision of robbed?bit signaling data embedded in the data stream. the buffer, while optimized for use with the ds2180a t1 transceiver, is also compatible with other transceiver devices. the ds2180a data sheet should serve as a valuable reference when designing with the ds2176. receive side timing figure 2 data synchronizationpcm buffer the ds2176 utilizes a 2?frame buffer (386 bits) to synchronize incoming pcm data to the system backplane clock. the buffer samples data at rser on the falling edge of rclk. output data appears at sser and is up-dated on the rising edge of sysclk. a rising edge at rmsync establishes receive side frame and multi-frame alignment. a rising edge at sfsync establishes system side frame alignment. the buffer depth is constantly monitored by onboard contention logic; a ?slip? occurs when the buffer is completely emptied or filled. slips automatically recenter the buffer to a one?frame depth and always occur on frame boundaries. slip correction capability the 2?frame buffer depth is adequate for most t?carrier applications where short?term jitter synchronization, rather than correction of significant frequency differences, is required. the ds2176 provides an ideal balance between total delay and slip correction capability. buffer recentering many applications require that the buffer be recentered during system power?up and/or initialization. forcing aln low recenters the buffer on the occurrence of the next frame sync boundary. a slip will occur during this recentering if the buffer depth is adjusted. if the depth is presently optimum, noadjustment (slip) occurs. slip is held low for 65 sysclk cycles when a slip occurs. slip is an active? low, open collector output.buffer depth monitoring smsync is a system side output pulse which indicates system side multiframe boundaries. the distance between rising edges at rmsync and smsync indicates the current buffer depth. slip direction and/or an impending slip condition may be determined by monitoring rmsync and smsync real time. smsync is held high for 65 sysclk cycles. clock select the device is compatible with two common backplane frequencies: 1.544 mhz, selected when sclksel=0; and 2.048 mhz, selected when sclksel=1. in 1.544 mhz applications the f?bit is downloaded from: http:///
ds2176 5 of 15 passed through the receive buffer and presented at sser immediately after the rising edge of the systemside frame sync. the f?bit is dropped in 2.048 mhz applications and the msb of channel 1 appears at sser one bit period after a rising edge at sfsync. sser is forced to 1 in all channels greater than 24. see figures 3 and 4. in 2.048 mhz applications (sclksel=1), the pcm buffer control logic establishes slip criteria different from that used in 1.544 mhz applications to compensate for the faster system-side read frequency. parallel compatibility the ds2176 is compatible with parallel and serial back-planes. channel 1 data appears at sser after a rising edge at sfsync as shown in figures 3 and 4 (serial applications, s/ p =1). the device utilizes a look?ahead circuit in parallel applications (s/ p =0). data is output 8 clocks earlier, allowing the user to convert parallel data eternally.system multiframe boundary timing (sysclk = 1.544 mhz) figure 3 downloaded from: http:///
ds2176 6 of 15 system multiframe boundary timing (sysclk = 2.048 mhz) figure 4 193s system multiframe timing figure 5 193e system multiframe timing figure 6 downloaded from: http:///
ds2176 7 of 15 signaling supervisionextraction in digital channel banks, robbed?bit signaling data is inserted into the lsb position of each channel during signaling frames. in 193s framing (fms=0) applications, a signaling data is inserted into frame 6 and b signaling data is inserted into frame 12. 193e framing (fms=1) includes two additional signaling bits: c signaling is inserted into frame 18 and d signaling is inserted into frame 24. this embedded signaling data is synchronized to system side timing (via the pcm buffer) before being extracted and presented at outputs a, b, c, and d. outputs a, b, c, and d are valid for each individual channel time and are repeated per channel for all frames of the multiframe. in 193s applications, outputs c and d contain the previous multiframe?s a and b data. signaling updates occur once per multiframe at the ris-ing edge of smsync unless prohibited by a freeze. freeze the signaling buffer allows the ds2176 to ?freeze? (pre-vent update of) signaling information during alarm or slip conditions. a slip condition or forcing sigh low freezes signaling; duration of the freeze is dependent on sm0 and sm1. updates will be unconditionally prohibited when sigh is held low. during freezing conditions ?old? data is recirculated in the output registers and appears at a, b, c and d.sigfrz is held high during the freeze condition, and returns low on the next signaling update. input to output delay of signaling data is equal to 1 multiframe (the depth of the signaling buffer) the current depth of the pcm buffer (1 frame approximately 1 frame). integrationsignaling integration is another feature of the ds2176; when selected, it minimizes the impact of random noise hits on the span and resultant robbed?bit signaling corruption. integration requires that per?channel signaling data be in the same state for two or more multiframes before appearing at a, b, c and d. sm0 and sm1 are used to select the degree of integration or to totally by-pass the feature. integration is limited to two multi-frames during slip or alarm conditions to minimize up-date delay. clear channel considerations the ds2176 does not merge the ?processed? signaling information with outgoing pcm data at sser; this assures integrity of data in clear channel applications. sbit8 indicates the lsb position of each channel; when combined with off?chip support logic, it allows the user to selectively re?insert robbed?bit signaling data into the outgoing data stream. downloaded from: http:///
ds2176 8 of 15 signaling supervision modes table 2 sm0 sm1 fms selected mode 0 0 0 193s framing, no integration, 1 multiframe freeze. 0 0 1 193e framing, no integration, 1 multiframe freeze. 0 1 0 193s framing, 2 multiframes integration and freeze. 0 1 1 193e framing, 2 multiframes integration and freeze. 1 0 0 1 193s framing, 5 multiframes integration, 2 multiframes freeze. 1 0 1 1 193e framing, 3 multiframes integration, 2 multiframes freeze. 1 1 0 193s framing, no integration, 1 multiframe freeze, replace robbed bitsignaling bits at sser with ones. 1 1 1 193e framing, no integration, 1 multiframe freeze, replace robbed bitsignaling bits at sser with ones. note:1. during slip or alarm conditions, integration is limited to two multiframes to minimize signaling delay. slip and signaling supervision logic timing figure 7 notes:1. integration feature disabled (sm0=sm1=0) in timing set shown. 2. depending on present buffer depth, forcing aln low may or may not cause a slip condition. downloaded from: http:///
ds2176 9 of 15 ds2176/ds2180a system applicationfigure 8 shows how the ds2180a t1 transceiver and ds2176 receive buffer interconnect in a typical application. serial 1.544 mhz backplane interface figure 8 downloaded from: http:///
ds2176 10 of 15 absolute maximum ratings* voltage on any pin relative to ground ?1.0v to +7.0v operating temperature 0 c to 70 c storage temperature ?55 c to +125 c soldering temperature 260 c for 10 seconds *this is a stress rating only and functional operation of the device at these or any other conditions abovethose indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameters symbol min typ max units notes logic 1 v ih 2.0 v dd +0.3 v logic 0 v il -0.3 +0.8 v supply v dd 4.5 5.5 v dc electrical characteristics (0c to 70c; v dd =5v 10 %) parameters symbol min typ max units notes supply current i dd 5 10 ma 1,2 input leakage i il -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma 3 output current @ 0.4v i ol +4.0 ma 4 output leakage i lo -1.0 +1.0 a 5 notes:1. tclk=rclk=1.544 mhz. 2. outputs open. 3. all outputs except slip , which is open collector. 4. all outputs.5. applies to slip when tri?stated. capacitance (t a =25 c) parameters symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf downloaded from: http:///
ds2176 11 of 15 ac electrical characteristics (0 c to 70 c; v dd =5v 10 %) parameters symbol min typ max units notes rclk period t rclk 250 648 ns rclk, sysclk riseand fall times t r, t f 20 ns rclk pulse width t rwh,t rwl 125 324 ns sysclk pulse width t swh,t swl 100 244 ns sysclk period t sysclk 200 488 ns rmsync setup torclk falling t sc 20 t rwh -5 ns sfsync setup tosysclk falling t sc 20 t swh -5 ns rmsync, sfsync, sigh , aln pulse width t pw 50 ns ns rser setup to rclkfalling t sd 50 ns rser hold from rclkfalling t hd 50 ns propagation delaysysclk to sser, a,b,c,d t pvd 100 ns propagation delaysysclk to smsync high t pss 75 ns propagation delaysysclk or rclk to slip low t ps 100 ns propagation delaysysclk to sigfrz low/high t psf 75 ns aln , sigh setup to sfsync rising t sr 500 ns notes:1. measured at v ih =2.0v, v il =0.8v, and 10 ns maximum rise and fall times. 2. output load capacitance = 100 pf. downloaded from: http:///
ds2176 12 of 15 receive ac diagram figure 9 system ac timing diagram figure 10 downloaded from: http:///
ds2176 13 of 15 ds2176 t1 receive buffer pkg 24-pin dim min max a in. mm 1.245 1.265 b in. mm 0.250 0.270 c in. mm 0.125 0.145 d in. mm 0.300 0.325 e in. mm 0.015 0.040 f in. mm 0.125 0.135 g in. mm 0.090 0.110 h in. mm 0.325 0.420 j in. mm 0.008 0.012 k in. mm 0.015 0.022 downloaded from: http:///
ds2176 14 of 15 DS2176Q inches dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 - b 0.026 0.033 b1 0.013 0.021 c 0.009 0.012 d 0.485 0.495 d1 0.450 0.456 d2 0.390 0.430 e 0.485 0.495 e1 0.450 0.456 e2 0.390 0.430 l1 0.060 - n 28 - e1 0.050 bsc ch1 0.042 0.048 downloaded from: http:///
ds2176 15 of 15 data sheet revision summarythe following represent the key differences between 04/19/95 and 06/13/97 version of the ds2176 data sheet. please review this summary carefully. 1. sync/clock relationship in timing diagram downloaded from: http:///

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